Farzana Ahmed Siddique

Farzana Ahmed Siddique

CS PhD Candidate @ UVA

She/her

I am a PhD Candidate in Computer Science at the University of Virginia, working with Professor Kevin Skadron. My research is in computer architecture, with a current focus on Processing-In-Memory (PIM), mainly, general-purpose PIM architecture design, benchmarking, and simulation frameworks.

I grew up in Bangladesh and completed my undergraduate studies in Computer Science and Engineering at Bangladesh University of Engineering and Technology (BUET). Since then, I have worked on topics ranging from automata processing on FPGA platforms to dynamic graph processing, but I am generally drawn to systems problems that sit at the intersection of performance and programmability.

You can reach out to me at farzana at virginia dot edu.

Education & Experiences

Education

PhD Candidate
Computer Science
University of Virginia
Present
BSc
Computer Science and Engineering
Bangladesh University of Engineering and Technology (BUET)
2011 – 2016
Higher Secondary Certificate (HSC)
Govt. Hazi Mohd. Mohsin College, Chittagong, Bangladesh
2008 – 2010
Secondary School Certificate (SSC)
B. M. S. Girls' High School and College, Chittagong, Bangladesh
2006 – 2008

Courses

  • Hardware Security
  • Compilers
  • Computer Architecture & Design
  • Operating Systems
  • Algorithms
  • Database Systems

Work Experience

Graduate Research Assistant
Department of Computer Science
University of Virginia (UVA)
Present
Software Engineer Intern
Google
Summer 2023
Software Engineer Intern
Meta Platforms Inc.
Summer 2022
Graduate Teaching Assistant
Department of Computer Science
University of Virginia (UVA)
Fall 2019 – Fall 2021
Software Engineer
iPay Systems Ltd.
Feb 2016 – Jan 2017
Undergraduate Research Assistant
Department of Computer Science and Engineering
Bangladesh University of Engineering and Technology (BUET)
Jul 2014 – Jul 2015

Publications

* indicates equal contribution

  • Architectural Modeling and Benchmarking for Digital DRAM PIM

    IEEE International Symposium on Workload Characterization (IISWC), 2024
    Farzana Ahmed Siddique, Deyuan Guo, Zhenxing Fan, Mohammadhosein Gholamrezaei, Morteza Baradaran, Alif Ahmed, Hugo Abbot, Kyle Durrer, Kumaresh Nandagopal, Ethan Ermovick, Khyati Kiyawat, Beenish Gul, Abdullah Mughrabi, Ashish Venkat, Kevin Skadron

  • GraphTango: A Hybrid Representation Format for Efficient Streaming Graph Updates and Analysis

    International Journal of Parallel Programming (IJPP), Volume 52, Issue 3, 2024
    Alif Ahmed*, Farzana Ahmed Siddique*, Kevin Skadron

  • Deterministic vs. Non-Deterministic Finite Automata in Automata Processing

    arXiv preprint arXiv:2210.10077, 2022
    Farzana Ahmed Siddique, Tommy James Tracy II, Nathan Brunelle, Kevin Skadron

  • A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem

    arXiv preprint arXiv:2111.04563, 2021
    Daehyeok Kim, Nikita Lazarev, Tommy Tracy, Farzana Ahmed Siddique, Hun Namkung, James C Hoe, Vyas Sekar, Kevin Skadron, Zhiru Zhang, Srinivasan Seshan

  • A Tale of Institutional Education in Bangladesh: Students' Perspective

    International Conference on Computer and Information Technology (ICCIT), 2016
    Muhammad Hussain Mahdi*, Nafisa Anzum*, Farzana Ahmed Siddique*, Mohammad Rashidujjaman Rifat, Kazi Shahidullah, A. B. M. Alim Al Islam

Course Projects

Security Implications of Value Prediction

For my hardware security course project, I designed and implemented threat models to attack one of the microarchitectural optimizations called value predictor. The hypotheses for the threat model was, existing value predictors are susceptible to targeted mis-prediction, and therefore can be mapped directly to the Load Value Injection (LVI) type attacks. For the hardware simulator, Gem5 has been used in this project.

Gem5, x86 Assembly
RISC-V Processor

Implemented a basic RV32I processor for the Computer Organization and Design course project. The processor uses single issue pipelining. Static branch prediction (predict branch as not taken) has been used to handle control hazard. In order to handle structural hazard, a memory arbiter has been implemented and used. For handling data hazard, a register tracker has been implemented and used. VHDL has been used for the implementation, ModelSim has been used for design simulation and Precision Synthesis for design synthesis.

VHDL, ModelSIM
Simple Shell

As a part of my graduate operating systems course, I implemented linux shell functionality using POSIX. I used C++ for the implementation. The shell functionality includes: executing commands, single input/output redirection, and pipelining.

C++
Threads & Barrier

Implemented a parallel, binary reduction algorithm to find the maximum number in a given list. For N numbers, the program uses log2(N) threads to cooperatively determine the maximum number in the list. No new threads have been spawned in each round—threads have been reused in all the rounds. A barrier has been implemented using posix binary semaphore to ensure synchronization among the threads.

C++
FAT32

Implemented a simplified C API for read-only operations on FAT32 files and directories.

C++
Hole Punch

Implemented C APIs to address the issue of communicating with a client which is hiding behind firewall or NAT. Built an external port forwarding mechanism similar to ssh reverse port-forwarding and SOCKS without the encryption overhead. This mechanism circumvents the restrictions of NAT and firewall and establishes the connection with outside port.

C

A Few Accomplishments

Outstanding Graduate Teaching Award

The Department of Computer Science, University of Virginia, presents awards to the graduate and undergraduate students in different categories. I got the end of the year (2021-2022) award in the category outstanding graduate teaching link.

Student Travel Grant

Computing Research Association-Women (CRA-W), USA awarded the travel grant for participating in the CRA-W Grad Cohort Workshop 2020.

ICCIT Conference Award

Our paper titled A Tale of Institutional Education in Bangladesh: Students' Perspective got the ICCIT, 2016 conference award in the track ITS: Information Technology and Systems.

Most Significant Contributor of The Year

I volunteered as a webmaster for creating the very first webpage of the BWCSE. This helped to present the activities of the BWCSE to the outside world, as a result BWCSE presented me the Most Significant Contributor of The Year, 2014 award link.

Anita Borg Student-Faculty Scholarship

I have received this scholarship during my undergrad in the year 2014. Because of this scholarship I was able to attend the Grace Hopper Celebration of Women in Computing (GHC), Phoenix, Arizona, USA, October 2014. This was the very first time an undergrad student from Bangladesh got this scholarship link.

Board Scholarship

I got this scholarship from the Chittagong, Bangladesh Education Board for my outstanding performance in the secondary school board examination.

Junior Scholarship

I got this scholarship from the Chittagong, Bangladesh Education Board for my outstanding performance in the junior school board examination.

Volunteer Works

Mentor
Computer Science Department Graduate Student Group at UVA
Mentoring a first year PhD student at the CS department of UVA
2022 – 2023
Media Chair
Association of Bangladeshi Students at UVA
Did photography and videography at the events arranged by Association of Bangladeshi Students at UVA
2021 – 2022
Mentor
Bangladeshi Women in Computer Science and Engineering (BWCSE)
Worked as a mentor for couple of undergrad female students
2017 – 2018
Event Director
Bangladeshi Women in Computer Science and Engineering (BWCSE)
Planned and organized events such as robotics competition, faculty/alumni talks, etc.
2015 – 2016
Webmaster
Bangladeshi Women in Computer Science and Engineering (BWCSE)
Designed and developed the webpage for the BWCSE
2014 – 2015